1. Field of the Invention
The present invention relates to a buffer circuit and more particularly, to a buffer circuit that suppresses fluctuation or deviation of the power supply voltage and the ground voltage caused by the logic state change of a specific signal, which is preferably used as an address buffer circuit outputting an output signal such as an address signal in a low impedance state to the memory section of a semiconductor memory device.
2. Description of the Related Art
FIG. 1 shows an example of the conventional address buffer circuits used for semiconductor memory devices.
As shown in FIG. 1, the prior-art address buffer circuit 102 is comprised of an input stage 104, first, second, third, and fourth inverter circuits 106, 108, 110, and 112, an Address Transition Detection (ATD) circuit 114, and a wave-synthesizing pulse generator circuit 116. Only the configuration for one bit of address is shown in FIG. 1 for the sake of simplification; however, it is needless to say that the circuit 102 actually includes a lot of the same configuration as shown in FIG. 1 according to the bit count of address.
The input stage 104 is a two-input NOR gate comprising two p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 131 and 132 connected in series and two n-channel MOSFETs 133 and 134 connected in parallel. The source of the p-channel MOSFET 131 is connected to the power supply line applied with a supply voltage of Vcc while the drain of the MOSFET 131 is connected to the source of the p-channel MOSFET 132. The drain of the p-channel MOSFET 132 is connected to the coupled drains of the n-channel MOSFETs 133 and 134. The coupled sources of the n-channel MOSFETs 133 and 134 are connected to the ground. The gates of the MOSFETs 132 and 133 are connected to each other, forming the first input terminal 104a of the input stage 104. An address signal ADIN, which is an input signal of the buffer circuit 102, is supplied from the outside of the circuit 102 to the first input terminal 104a. The coupled gates of the MOSFETs 131 and 134 form the second input terminal 104b of the input stage 104. A chip enable signal CEB is supplied to the second input terminal 104b from the outside of the circuit 102. The coupled drains of MOSFETs 132, 133, and 134 constitute the output terminal 104c of the input stage 104.
When the chip enable signal CEB is at a specific logic level, the address signal ADIN is taken into the input stage 104 and the output signal having an opposite logic level to the signal ADIN is outputted at the output terminal 104c. The output signal thus outputted is then supplied to the fourth inverter circuit 112.
The first, second, third, and fourth inverter circuits 106, 108, 110, and 112 have substantially the same configuration. Therefore, the configuration of the fourth inverter circuit 112 is explained below and the detailed description about the first, second, third inverter circuits 106, 108, and 110 is omitted by adding the same reference symbols to those of the circuit 112 except for the suffix letters.
The fourth inverter circuit 112 is comprised of a p-channel MOSFET 135a and an n-channel MOSFET 136a whose drains are coupled together, which is a Complementary MOS (CMOS) inverter. The source of the MOSFET 135a is connected to the power supply line of Vcc. The source of the MOSFET 136a is connected to the ground. The gates of the MOSFETs 135a and 136a are coupled together, forming the input terminal 112a of the circuit 112. The input terminal 112a is connected to the output terminal 104c of the input stage 104. The coupled drains of the MOSFETs 135a and 136a form the output terminal 112b of the circuit 112.
The fourth inverter circuit 112 generates at the output terminal 112b an output signal having an opposite logic level to the output signal from the input stage 104. The output signal of the circuit 112 thus generated is then supplied to the ATD circuit 114 as the ATD input signal ATDIN and at the same time, it is supplied to the second and third inerter circuits 108 and 110. As shown in FIG. 1, the ATD input signal ATDIN is also supplied to specific circuits (not shown) provided outside the address buffer circuit 102.
The second inverter circuit 108, which has substantially the same configuration as the fourth inverter circuit 112, has an input terminal 108a formed by the coupled gates of a p-channel MOSFET 135b and an n-channel MOSFET 136b and an output terminal 108b formed by the coupled drains thereof. The input terminal 108a is connected to the output terminal 112b of the fourth inverter circuit 112. The circuit 108 generates at its output terminal 108b an output signal having an opposite logic level to the output signal from the fourth inverter circuit 112 supplied to the input terminal 108a. The output signal of the circuit 108 is the inverted address signal BAR, which is one of the two output signals of the address buffer circuit 102. The signal BAR is then supplied to a decoder circuit or circuits (not shown) provided outside the buffer circuit 102.
The third inverter circuit 110, which has substantially the same configuration as the fourth inverter circuit 112, has an input terminal 110a formed by the coupled gates of a p-channel MOSFET 135c and an n-channel MOSFET 136c and an output terminal 110b formed by the coupled drains thereof. The input terminal 110a is connected to the output terminal 112b of the fourth inverter circuit 112. The circuit 110 generates at its output terminal 110b an output signal having an opposite logic level to the output signal from the fourth inverter circuit 112 supplied to the input terminal 110a. The output signal of the circuit 110 is then supplied to the first inverter circuit 106.
The first inverter circuit 106, which has substantially the same configuration as the fourth inverter circuit 112, has an input terminal 106a formed by the coupled gates of a p-channel MOSFET 135d and an n-channel MOSFET 136d and an output terminal 106b formed by the coupled drains thereof. The input terminal 106a is connected to the output terminal 110b of the third inverter circuit 110. The circuit 106 generates at its output terminal 106b an output signal having an opposite logic level to the output signal from the third inverter circuit 110 supplied to the input terminal 106a. The output signal of the circuit 106 is the address signal TRUE, which is the other of the two output signals of the address buffer circuit 102. The signal TRUE is then supplied to the decoder circuit or circuits (not shown) provided outside the buffer circuit 102.
The ATD circuit 114 is supplied with the ATD input signal ATDIN outputted from the fourth inverter circuit 112. The circuit 114 detects the logic level change of the signal ATDIN (i. e., address transition) and then, outputs the ATD output signal ATDOUT to the wave-synthesizing pulse generator circuit 116.
The pulse generator circuit 116 generates a data latch signal DTL including pulses varying from the logic high level to the logic low level based on the signal ATDOUT from the ATD circuit 114, and outputs the signal DTL to specific circuits provided outside the buffer circuit 102.
The address signal TRUE, which is outputted from the first inverter circuit 106, has a waveform corresponding to that of the address signal ADIN supplied to the input stage 104 of the buffer circuit 102. Also, the inverted address signal BAR, which is outputted from the second inverter circuit 108, has an inverted waveform of the signal TRUE. In other words, the signal BAR has an inverted logic level to the signal TRUE. The address signal TRUE and the inverted address signal BAR are supplied to the memory section (not shown) located outside the buffer circuit 102 through the decoder circuit or circuits (not shown) The data latch signal DTL, which is outputted from the pulse generator circuit 116, is supplied to the memory section as well.
Data signals are outputted from the respective memory cells in the memory section according to the address signal TRUE and the inverted address signal BAR. A latch circuit or circuits (now shown) provided in the memory section latches/latch the data signals thus outputted so as to be synchronized with the data latch signal DTL.
FIG. 2 shows the waveforms of the address signal ADIN, the address signal TRUE, the inverted address signal BAR, the power supply current flowing through the power supply line, the, ground current flowing through the ground line, the power supply voltage, and the ground voltage in the prior-art address buffer circuit 102 shown in FIG. 1.
As shown in FIG. 2, the address signal ADIN supplied to the buffer circuit 102 is turned from the logic low (L) level to the logic high (H) level at the time T101 and then, returned from the logic high level to the logic low level at the time T102. According to this change of the signal ADIN, the address signal TRUE is turned from the logic low level to the logic high level at the time T101 and then, returned from the logic high level to the logic low level at the time T102. On the other hand, the inverted address signal BAR is turned from the logic high level to the logic low level at the time T101 and then, returned from the logic low level to the logic high level at the time T102.
As known well, an inverter circuit formed by MOSFETs with the CMOS configuration has a tendency that a large current flows when the input signal (and the output signal as well) is switched between the logic high and low levels. In particular, since the first and second inverter circuits 106 and 108 have high current driving capabilities, the tendency appears remarkably. Specifically, a large current tends to flow through the MOSFETs 135b and 136b in the second inverter circuit 108 and a large current tends to flow through the MOSFETs 135d and 136d in the first inverter circuit 106 at the switching time of the input and output signals between the logic high and low levels. Accordingly, as shown by the curved lines 118 and 120 in FIG. 2, the power supply current and the ground current vary largely like a spike at the times T101 and T102 at which the signals TRUE and BAR are switched between the logic high and low levels. Consequently, as shown by the symbols R101 and R102 in FIG. 2, the power supply voltage temporarily lowers while the ground voltage temporarily rises at the times T101 and T102.
As described previously, the prior-art address buffer circuit 102 actually includes a lot of the configuration shown in FIG. 1 according to the bit count of address. Also, the bit count of address is huge in recent years and thus, the count of the inverter circuits in the circuit 102 is huge, in which all the inverter circuits typically operates simultaneously with the logic state change of the address signal ADIN. As a result, the deviation or fluctuation of the power supply voltage and the ground voltage is very large and unable to be ignored.
Generally, a semiconductor memory device includes other circuits than the address buffer circuit 102 that commonly use the power supply and ground lines for the circuit 102. Thus, the above-described fluctuation or deviation of the power supply and ground voltages causes unstable operation and/or malfunction of these circuits.
Accordingly, an object of the present invention is to provide a buffer circuit that suppresses the fluctuation or deviation of the power supply voltage and the ground voltage that are caused by the logic state change of an address signal applied thereto.
Another object of the present invention is to provide a buffer circuit that prevents unstable operation and/or malfunction of other circuits using commonly the power supply and ground lines for the buffer circuit without any complicated circuit configuration.
The above objects together with others specifically mentioned will become clear to those skilled in the art from the following description.
A buffer circuit according to the present invention comprises:
(a) a first inverter circuit including a first MOSFET having a channel of a first conductivity type and a second MOSFET having a channel of a second conductivity type opposite to the first conductivity type;
a gate of the first MOSFET and a gate of the second MOSFET being coupled together, forming an input terminal of the first inverter circuit;
a first input signal at a first logic state being applied to the input terminal of the first inverter circuit;
one end of the channel of the first MOSFET and one end of the channel of the second MOSFET being coupled together, forming an output terminal of the first inverter circuit:
(b) a second inverter circuit including a third MOSFET having a channel of the first conductivity type and a fourth MOSFET having a channel of the second conductivity type;
a gate of the third MOSFET and a gate of the fourth MOSFET being coupled together, forming an input terminal of the second inverter circuit;
a second input signal at a second logic state opposite to the first logic state being applied to the input terminal of the second inverter circuit;
one end of the channel of the third MOSFET and one end of the channel of the fourth MOSFET being coupled together, forming an output terminal of the second inverter circuit:
(c) an equalization circuit for equalizing the first output signal of the first inverter circuit and the second output signal of the second inverter circuit to each other;
the equalization circuit including a fifth MOSFET having a channel of the first conductivity type and a sixth MOSFET having a channel of the second conductivity type;
one end of the channel of the fifth MOSFET and one end of the channel of the sixth MOSFET being coupled together to be connected to the output terminal of the first inverter circuit;
the other end of the channel of the fifth MOSFET and the other end of the channel of the sixth MOSFET being coupled together to be connected to the output terminal of the second inverter circuit;
gates of the fifth and sixth MOSFETs being respectively applied with control signals at opposite logic levels, thereby setting the equalization circuit in a high-impedance state or a low-impedance state;
(d) a first switching circuit for connecting the other end of the channel of the first MOSFET to a first voltage line or disconnecting it from the first voltage line;
the first switching circuit including a seventh MOSFET having a channel of the first conductivity type;
one end of the channel of the seventh MOSFET being connected to the other end of the channel of the first MOSFET;
the first switching circuit being switched by a control signal applied to a gate of the seventh MOSFET;
(e) a second switching circuit for connecting the other-end of the channel of the second MOSFET to a second voltage line or disconnecting it from the second voltage line;
the second switching circuit including an eighth MOSFET having a channel of the second conductivity type;
one end of the channel of the eighth MOSFET being connected to the other end of the channel of the second MOSFET;
the second switching circuit being switched by a control signal applied to a gate of the eighth MOSFET;
(f) a third switching circuit for connecting the other end of the channel of the third MOSFET to the first voltage line or disconnecting it from the first voltage line;
the third switching circuit including a ninth MOSFET having a channel of the first conductivity type;
one end of the channel of the ninth MOSFET being connected to the other end of the channel of the third MOSFET; and
the third switching circuit being switched by a control signal applied to a gate of the ninth MOSFET;
(g) a fourth switching circuit for connecting the other end of the channel of the fourth MOSFET to the second voltage line or disconnecting it from the second voltage line;
the fourth switching circuit including a tenth MOSFET having a channel of the second conductivity type;
one end of the channel of the tenth MOSFET being connected to the other end of the channel of the fourth MOSFET;
the fourth switching circuit being switched by a control signal applied to a gate of the tenth MOSFET;
(h) the equalization circuit being set in the high-impedance state, when the first switching circuit connects the other end of the channel of the first MOSFET to the first voltage line, the second switching circuit connects the other end of the channel of the second MOSFET to the second voltage line, the third switching circuit connects the other end of the channel of the third MOSFET to the first voltage line, and the fourth switching circuit connects the other end of the channel of the fourth MOSFET to the second voltage line;
the first inverter circuit generating a first output signal in the second logic state at its output terminal and the second inverter circuit generating a second output signal in the first logic state at its output terminal; and
(i) the equalization circuit being set in the low-impedance state, when the first switching circuit disconnects the other end of the channel of the first MOSFET from the first voltage line, the second switching circuit disconnects the other end of the channel of the second MOSFET from the second voltage line, the third switching circuit disconnects the other end of the channel of the third MOSFET from the first voltage line, and the fourth switching circuit disconnects the other end of the channel of the fourth MOSFET from the second voltage line;
the output terminals of the first and second inverter circuits being connected to each other by way of the equalization circuit, resulting in the first and second output signals of the first and second inverter circuits being in an approximately intermediate or medium logic state between the first and second logic states.
With the buffer circuit according to the present invention, as describe above, the first switching circuit is provided for connecting/disconnecting the other end of the channel of the first MOSFET to the first voltage line, the second switching circuit is provided for connecting/disconnecting the other end of the channel of the second MOSFET to the second voltage line, the third switching circuit is provided for connecting/disconnecting the other end of the channel of the third MOSFET to the first voltage line, and the fourth switching circuit is provided for connecting/disconnecting the other end of the channel of the fourth MOSFET to the second voltage line. Moreover, the equalization circuit is provided for equalizing the first output signal of the first inverter circuit and the second output signal of the second inverter circuit to each other.
If the first switching circuit connects the other end of the channel of the first MOSFET to the first voltage line, the second switching circuit connects the other end of the channel of the second MOSFET to the second voltage line, the third switching circuit connects the other end of the channel of the third MOSFET to the first voltage line, and the fourth switching circuit connects the other end of the channel of the fourth MOSFET to the second voltage line, the equalization circuit is set in the low-impedance state. Therefore, the first and second inverters operate normally and as a result, the first inverter circuit generates the first output signal in the second logic state at its output terminal and the second inverter circuit generates the second output signal in the first logic state at its output terminal.
On the other hand, if the first switching circuit disconnects the other end of the channel of the first MOSFET from the first voltage line, the second switching circuit disconnects the other end of the channel of the second MOSFET from the second voltage line, the third switching circuit disconnects the other end of the channel of the third MOSFET from the first voltage line, and the fourth switching circuit disconnects the other end of the channel of the fourth MOSFET from the second voltage line, the first and second inverters are unable to operate normally.
In this case, unwanted signals having opposite logic states are generated at the output terminals of the first and second inverter circuits due to the parasitic capacitances existing in the neighborhood of the gates of the first and second MOSFETs of the first inverter circuit and the gates of the third and fourth MOSFETs of the second inverter circuit This is because the input terminal of the first inverter circuit is applied with the first input signal at the first logic state while the input terminal of the second inverter circuit is applied with the second input signal at the second logic state opposite to the first logic state.
At this time, the equalization circuit is set in the low-impedance state and thus, the output terminals of the first and second inverter circuits are connected to each other by way of the equalization circuit. Therefore, the first and second output signals of the first and second inverter circuits are in an approximately intermediate or medium logic state between the first and second logic states.
Accordingly, if the first and second inverter circuits need not output their output signals, the first and second output signals of the first and second inverter circuits can be set in an approximately intermediate or medium logic state between the first and second logic states by controlling the first to fourth switching circuits and the equalization circuit in the above-described manner. Thereafter, if the first and second inverter circuits are required to output their output signals, the first and second output signals of the first and second inverter circuits are turned to the first or second logic state (i.e., the logic high or low level) from the intermediate or medium state. This means that the output signals of the first and second inverters have narrow variation ranges of voltage, which narrows the variation ranges of the power supply current. Thus, the fluctuation or deviation of the power supply voltage and the ground voltage can be effectively suppressed.
Because of the suppressed fluctuation or deviation of the power supply voltage and the ground voltage, unstable operation and/or malfunction of other circuits using commonly the power supply and ground lines for the buffer circuit can be prevented.
Since it is sufficient that the first to fourth switching circuits and the equalization circuit are additionally provided, no complicated circuit configuration is required.